The present invention concerns circuit testing. More particularly, the present invention relates to built-in-self-test (BIST) circuitry for testing a phase locked loop (PLL) circuit.
Once manufactured, it is necessary to test very large scale integrated (VLSI) circuits to detect processing faults which could impair or inhibit correct operation of the circuit. Typically, this has been done by the external application of various test stimuli to inputs of the circuit and checking the actual response with an expected response.
As the complexity of some circuits increase, it is increasingly difficult to thoroughly test such circuits using just the external application of test stimuli. To facilitate testing of these more complex circuits, built-in self-test (BIST) circuitry is often included within the manufactured circuit to serve as an aid in the testing process. See for example, Edward J. McCluskey, Built-In-Self-Test Techniques, IEEE Design & Test, Volume 2, Number 2, April 1985, pages 21-28. See also, Edward J. McCluskey, Built-In Self-Test Structures, IEEE Design & Test, Volume 2, Number 2, April 1985, pages 29-36.